Semiconductor integrated circuit device

ABSTRACT

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2008-308585 filed onDec. 3, 2008 and Japanese Patent Application No. 2009-188913 filed onAug. 18, 2009 each including the specification, drawings and abstractare incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a technique effectively applied tointerconnection technology between a pad electrode on a semiconductorchip in a semiconductor integrated circuit device (semiconductor deviceor electronic circuit device) and an external device.

Published Japanese translation of a PCT application No. 2004-533711(Patent Document 1) or U.S. Pat. No. 6,534,863 (Patent Document 2)discloses a technique for bonding a gold wire to a pad comprised of aTaN (bonding layer)/Ta (barrier layer)/Cu (seed layer)/Ni (firstelectroplated layer)/Au (second electroplated layer), or the like fromthe lower layer side, instead of an aluminum pad whose surface tends tobe easily oxidized, in a semiconductor device with a copper wiringstructure.

RELATED ART DOCUMENTS Patent Documents [Patent Document 1]

-   Published Japanese translation of a PCT application No. 2004-533711

[Patent Document 2]

-   U.S. Pat. No. 6,534,863

SUMMARY OF THE INVENTION

In semiconductor circuit devices for vehicle use or the like, analuminum pad on a semiconductor chip and an external device aregenerally coupled to each other by wire bonding or the like using a goldwire and the like for the convenience of mounting. Such a semiconductorintegrated circuit device, however, causes connection failure, such asKirkendall Void, due to the interaction between aluminum and gold in usefor a long time at a relatively high temperature (about 150 degrees. C).

The invention of the present application is to solve the forgoingproblems.

It is an object of the invention to provide a semiconductor integratedcircuit device with high reliability.

The above, other objects, and novel features of the invention willbecome apparent from the description of the present specification withreference to the accompanying drawings.

The following briefly describes the summary of representativeembodiments of the invention disclosed in the present application.

That is, in the invention of the present application, a gold-basedsurface metal layer is provided over an aluminum or copper-based bondingpad on a semiconductor chip via a barrier metal film. The bonding pad isa part of a semiconductor integrated circuit device (semiconductordevice or electron circuit device). And a gold or copper-based bondingwire connection portion or bonding ball is provided for connection to anexternal portion.

The effects obtained by the representative embodiments of the inventiondisclosed in the present application will be briefly described in thefollowing.

That is, since the gold or copper-based bonding wire or bonding ball isbonded to the aluminum or copper-based bonding pad via the gold-basedsurface film or layer, even the use of the semiconductor integratedcircuit device for a long time at a relatively high temperature does notcause the failure of connection due to the interaction between gold andaluminum or the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a longitudinal device structural diagram (corresponding to apart enclosed by a broken line shown in FIG. 3) of a semiconductor chipin a semiconductor integrated circuit device at the time of completionof a pad opening step according to one embodiment of the presentapplication,

FIG. 2 is a process flowchart showing the flow from the pad opening stepto a wire bonding process during a manufacturing procedure of thesemiconductor integrated circuit device in the embodiment of the presentapplication,

FIG. 3 is a process flowchart showing a device section (at the time ofcompletion of the pad opening step) of the semiconductor chip(corresponding to a section taken along the line X-X′ of FIG. 18) of thesemiconductor integrated circuit device in the embodiment of the presentapplication,

FIG. 4 is a process flowchart showing a device section (in a barrierfilm formation step) of the semiconductor chip (corresponding to asection taken along the line X-X′ of FIG. 19) of the semiconductorintegrated circuit device in the embodiment of the present application,

FIG. 5 is a process flowchart showing a device section (in a resist filmapplication step) of the semiconductor chip (corresponding to a sectiontaken along the line X-X′ of FIG. 20) of the semiconductor integratedcircuit device in the embodiment of the present application,

FIG. 6 is a process flowchart showing a device section (in a resist filmopening step) of the semiconductor chip (corresponding to a sectiontaken along the line X-X′ of FIG. 21) of the semiconductor integratedcircuit device in the embodiment of the present application,

FIG. 7 is a process flowchart showing a device section (in a goldplating step) of the semiconductor chip (corresponding to a sectiontaken along the line X-X′ of FIG. 22) of the semiconductor integratedcircuit device in the embodiment of the present application,

FIG. 8 is a process flowchart showing a device section (in a resistremoval step) of the semiconductor chip (corresponding to a sectiontaken along the line X-X′ of FIG. 23) of the semiconductor integratedcircuit device in the embodiment of the present application,

FIG. 9 is a process flowchart showing a device section (in a barriermetal removal step) of the semiconductor chip (corresponding to asection taken along the line X-X′ of FIG. 24) of the semiconductorintegrated circuit device in the embodiment of the present application,

FIG. 10 is a top view of the semiconductor chip of the semiconductorintegrated circuit device in the embodiment of the present application,corresponding to FIG. 9,

FIG. 11 is a top view of the semiconductor integrated circuit device inthe embodiment of the present application,

FIG. 12 is an exemplary cross-sectional view corresponding to a partenclosed by a broken line shown in FIG. 11,

FIG. 13 is an exemplary cross-sectional view showing an example in whichthe order of wire bonding is changed from that in FIG. 12,

FIG. 14 is an exemplary cross-sectional view showing an example in whicha wiring board is replaced by other electronic elements on the wiringboard in FIG. 12,

FIG. 15 is an exemplary cross-sectional view showing an example in whicha target part of the semiconductor chip to be die-bonded is replaced byanother electronic element (flip-chip bonded) on the wiring board inFIG. 12,

FIG. 16 is a device cross-sectional view of the semiconductor chip (atthe time of completion of a wafer processing step) (corresponding to thesection taken along the line X-X′ of FIG. 25) of the semiconductorintegrated circuit device according to another embodiment of the presentapplication (in an example where two layered polyimide film is providedas an additional final passivation film),

FIG. 17 is a top view of the semiconductor chip of the semiconductorintegrated circuit device in the embodiment of the present application,corresponding to FIG. 3,

FIG. 18 is an enlarged top view (whose corresponding cross-sectionalview is shown in FIG. 3) of a part enclosed by a broken line in FIG. 17,

FIG. 19 is an enlarge top view of the part enclosed by the broken linein FIG. 17 in the step corresponding to FIG. 4,

FIG. 20 is an enlarge top view of the part enclosed by the broken linein FIG. 17 in the step corresponding to FIG. 5,

FIG. 21 is an enlarge top view of the part enclosed by the broken linein FIG. 17 in the step corresponding to FIG. 6,

FIG. 22 is an enlarge top view of the part enclosed by the broken linein FIG. 17 in the step corresponding to FIG. 7,

FIG. 23 is an enlarge top view of the part enclosed by the broken linein FIG. 17 in the step corresponding to FIG. 8,

FIG. 24 is an enlarge top view of the part enclosed by the broken linein FIG. 17 in the step corresponding to FIG. 9,

FIG. 25 is an enlarged top view of the step corresponding to FIG. 16,

FIG. 26 is an explanatory cross-sectional view for explaining problemsof nonelectrolytic gold plating on a nickel surface,

FIG. 27 is an enlarge view of atop surface of a wafer (square pad in afirst example) showing a state of a wafer probe test process in themanufacturing procedure of the semiconductor integrated circuit devicein the embodiment of the present application,

FIG. 28 is an enlarge view of the top surface of the wafer (square padin the first example) at the time of completion of the wire bondingprocess in the example corresponding to FIG. 27,

FIG. 29 is an enlarge view of a top surface of another wafer (normaltype rectangular pad in a second example) showing the state of the waferprobe test process in the manufacturing procedure of the semiconductorintegrated circuit device in the embodiment of the present application,

FIG. 30 is an enlarge view of the top surface of the wafer (normalrectangular pad in the second example) at the time of completion of thewire bonding process in the example corresponding to FIG. 29,

FIG. 31 is an enlarge view of a top surface of a further wafer (modifiedrectangular pad in a third example) showing the state of the wafer probetest process in the manufacturing procedure of the semiconductorintegrated circuit device in the embodiment of the present application,

FIG. 32 is an enlarge view of the top surface of the wafer (modifiedrectangular pad in the third example) at the time of completion of thewire bonding process in the example corresponding to FIG. 31,

FIG. 33 is a local exemplary cross-sectional view of an aluminum pad anda bonding wire for explaining Kirkendall Void generated in bondingbetween aluminum and gold,

FIG. 34 is a local cross-sectional view showing one of various examples(normal mode) of a bonded state of the bonding wire on the pad at thesemiconductor integrated circuit device in the embodiment of the presentapplication,

FIG. 35 is a local cross-sectional view showing one of various examples(lateral sliding mode 1) of a bonded state of the bonding wire on thepad at the semiconductor integrated circuit device in the embodiment ofthe present application,

FIG. 36 is a local cross-sectional view showing one of various examples(lateral sliding mode 2) of a bonded state of the bonding wire on thepad at the semiconductor integrated circuit device in the embodiment ofthe present application,

FIG. 37 is a local cross-sectional view for explaining the relationshipamong various dimensions of a bonded structure of the bonding wire onthe pad at the semiconductor integrated circuit device in the embodimentof the present application,

FIG. 38 is an entire top view of the semiconductor integrated circuitdevice (wire bonding type BGA) at the time of completion of a packagingprocess in the embodiment of the present application (omittingillustration of a resin sealing member for easy understanding),

FIG. 39 is an exemplary cross-sectional view of FIG. 38,

FIG. 40 is an entire top view of the semiconductor integrated circuitdevice (QFP: Quad Flat Package) at the time of completion of a packagingprocess in the embodiment of the present application (omittingillustration of an upper half part of the resin sealing member for easyunderstanding),

FIG. 41 is an exemplary cross-sectional view of FIG. 40,

FIG. 42 is an entire top view of the semiconductor integrated circuitdevice (flip-chip type BGA) at the time of completion of a packagingprocess in the embodiment of the present application,

FIG. 43 is an exemplary cross-sectional view of FIG. 42,

FIG. 44 is an enlarged cross-sectional view of a part enclosed by abroken line in FIG. 43,

FIG. 45 is a cross-sectional view of the periphery of the pad forexplaining one type of under bumb metal structure (two-layeredstructure) in the semiconductor integrated circuit device of theembodiment of the present application,

FIG. 46 is a cross-sectional view of the periphery of the pad in amodified example of FIG. 45, and

FIG. 47 is a cross-sectional view of the periphery of the pad forexplaining another type of underbumb metal structure (three ormore-layered multilayer structure) in the semiconductor integratedcircuit device of the embodiment of the present application.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Summary of PreferredEmbodiments

First, representative preferred embodiments of the invention disclosedin the present application will be summarized below.

1. A semiconductor integrated circuit device includes: (a) an aluminumor copper-based pad electrode provided over a device surface of asemiconductor chip; (b) a barrier metal film provided over the padelectrode; (c) a surface metal film provided over the barrier metalfilm, and including gold as a principal component; and (d) a bondingball or bonding wire bonded to the surface metal film, and includinggold or copper as a principal component.

2. In the semiconductor integrated circuit device according to Item 1, athickness of the surface metal film is larger than that of the barriermetal film.

3. In the semiconductor integrated circuit device according to Item 1 or2, the surface metal film is formed by electrolytic plating orsputtering.

4. In the semiconductor integrated circuit device according to any oneof Items 1 to 3, the surface metal film is formed by the electrolyticplating.

5. In the semiconductor integrated circuit device according to any oneof Items 1 to 4, an area of the surface metal film is larger than thatof an opening of an insulating film over the pad electrode.

6. In the semiconductor integrated circuit device according to any oneof Items 1 to 5, an area of the pad electrode is larger than that of thesurface metal film.

7. In the semiconductor integrated circuit device according to any oneof Items 1 to 6, the opening of the insulating film over the padelectrode is located within the surface metal film as viewed planarly.

8. The semiconductor integrated circuit device according to any one ofItems 1 to 7, the surface metal film is located within the pad electrodeas viewed planarly.

9. The semiconductor integrated circuit device according to any one ofItems 1 to 4, the surface metal film extends up to an area without thepad electrode.

10. In the semiconductor integrated circuit device according to any oneof Items 1 to 9, the bonding ball is a ball portion of a bonding wire.

11. In the semiconductor integrated circuit device according to any oneof Items 1 to 10, the bonding ball is comprised of a member includinggold as a principal component.

12. In the semiconductor integrated circuit device according to any oneof Items 1 to 10, the bonding ball is comprised of a member includingcopper as a principal component.

13. In the semiconductor integrated circuit device according to any oneof Items 1 to 12, the pad electrode is an aluminum or copper-based padelectrode.

14. In the semiconductor integrated circuit device according to any oneof Items 1 to 13, the barrier metal film includes titanium as aprincipal component.

15. In the semiconductor integrated circuit device according to any oneof Items 1 to 13, the barrier metal film includes one selected from thegroup comprising titanium, chrome, titanium nitride, and tungstennitride as a principal component.

16. The semiconductor integrated circuit device according to any one ofItems 1 to 15 further includes (e) a seed metal film provided betweenthe barrier metal film and the surface metal film.

17. In the semiconductor integrated circuit device according to item 16,the seed metal film includes palladium as a principal component.

18. In the semiconductor integrated circuit device according to item 16,the seed metal film includes one selected from the group comprisingcopper, gold, nickel, platinum, rhodium, molybdenum, tungsten, chrome,and tantalum.

19. In the semiconductor integrated circuit device according to any oneof Items 1 to 18, the pad electrode has a substantially square shape asviewed planarly.

20. In the semiconductor integrated circuit device according to any oneof Items 1 to 18, the pad electrode has a substantially rectangularshape as viewed planarly.

Next, other preferred embodiments of the invention disclosed in thepresent application will be summarized below.

1. A semiconductor integrated circuit device includes: (a) a wiringboard; (b) a first semiconductor chip fixed to the wiring board or to afirst electronic element provided over the wiring board; (c) an aluminumor copper-based pad electrode provided over a device surface of thefirst semiconductor chip; (d) a barrier metal film provided over the padelectrode; (e) a seed metal film provided over the barrier metal film;(f) a surface metal film provided over the seed metal film byelectrolytic plating and including gold as a principal component; (g) anexternal metal electrode provided outside the first semiconductor chip;and (h) a bonding wire provided for coupling the surface metal film tothe external metal electrode, and including gold as a principalcomponent.

2. In the semiconductor integrated circuit device according to Item 1,the pad electrode is an aluminum-based pad electrode.

3. In the semiconductor integrated circuit device according to Item 1 or2, the barrier metal film includes titanium as a principal component.

4. In the semiconductor integrated circuit device according to any oneof Items 1 to 3, the seed metal film includes palladium as a principalcomponent.

5. In the semiconductor integrated circuit device according to any oneof Items 1, 2, and 4, the barrier metal film includes one selected fromthe group comprising titanium, chrome, titanium nitride, and tungstennitride.

6. In the semiconductor integrated circuit device according to any oneof Items 1 to 3, and 5, the seed metal film includes one selected fromthe group comprising copper, gold, nickel, platinum, rhodium,molybdenum, tungsten, chromium, and tantalum as a principal component.

7. In the semiconductor integrated circuit device according to any oneof Items 1 to 6, the first semiconductor chip is fixed to the wiringboard.

8. In the semiconductor integrated circuit device according to any oneof Items 1 to 6, the first semiconductor chip is fixed to the firstelectronic element over the wiring board.

9. In the semiconductor integrated circuit device according to any oneof Items 1 to 8, the external metal electrode is located over the wiringboard.

10. In the semiconductor integrated circuit device according to any oneof Items 1 to 8, the external metal electrode is located over the firstelectronic element located over the wiring board.

11. In the semiconductor integrated circuit device according to any oneof Items 1 to 10, the bonding wire has a first bonding point located onthe surface metal film side.

12. In the semiconductor integrated circuit device according to any oneof Items 1 to 10, the bonding wire has a second bonding point located onthe surface metal film side.

13. In the semiconductor integrated circuit device according to any oneof Items 1 to 12, a metal film including gold, silver, or palladium as aprincipal component is provided at a surface of the external metalelectrode.

14. A method for manufacturing a semiconductor integrated circuit deviceis provided. The semiconductor integrated circuit device includes: (a) awiring board; (b) a first semiconductor chip fixed to the wiring boardor to a first electronic element provided over the wiring board; (c) analuminum or copper-based pad electrode provided over a device surface ofthe first semiconductor chip; (d) a barrier metal film provided over thepad electrode; (e) a seed metal film provided over the barrier metalfilm; (f) a surface metal film provided over the seed metal film andincluding gold as a principal component; (g) an external metal electrodeprovided outside the first semiconductor chip; and (h) a bonding wireprovided for coupling the surface metal film and the external metalelectrode to each other, and including gold as a principal component.The method includes the steps of: (I) forming the seed metal film overthe substantially entire surface of a semiconductor wafer; (II) forminga resist film with an opening over the seed metal film; and (III)forming the surface metal film by forming a plated layer at the openingby electrolytic plating.

Further, other preferred embodiments of the invention disclosed in thepresent application will be summarized below.

1. A semiconductor integrated circuit device includes: (a) an aluminumor copper-based pad electrode provided over a device surface of asemiconductor chip; (b) a barrier metal film provided over the padelectrode; (c) a surface metal film provided over the barrier metal filmby electrolytic plating, and including gold as a principal component;and (d) a bonding ball, or bonding wire provided over the surface metalfilm and including gold or copper as a principal component.

2. In the semiconductor integrated circuit device according to Item 1,the pad electrode is an aluminum-based pad electrode.

3. In the semiconductor integrated circuit device according to Item 1 or2, the barrier metal film includes titanium as a principal component.

4. The semiconductor integrated circuit device according to any one ofItems 1 to 3 further includes: (e) a seed metal film provided betweenthe barrier metal film and the surface metal film.

5. In the semiconductor integrated circuit device according to Item 4,the seed metal film includes palladium as a principal component.

6. In the semiconductor integrated circuit device according to any oneof Items 1, 2, 4, and 5, the barrier metal film includes one selectedfrom the group comprising titanium, chrome, titanium nitride, andtungsten nitride as a principal component.

7. In the semiconductor integrated circuit device according to Item 4 or6, the seed metal film includes one selected from the group comprisingcopper, gold, nickel, platinum, rhodium, molybdenum, tungsten, chromium,and tantalum as a principal component.

[Explanation of Description Format, Basic Terms, and Usage in PresentApplication]

1. The description of the following preferred embodiments in the presentapplication may be divided into sections for convenience if necessary,but these embodiments are not separated from each other independentlyexcept when specified otherwise. One of the embodiments hasrelationships with respect to the other, including each part of acorresponding single example, a detailed description of a part of theother, and a modified example or the like of a part or all of the other.The repeated description of the same part will be omitted in principle.Further, each component of the embodiments is not essential except whenspecified otherwise, except when limited to the specific number of thecomponents in theory, and except when clearly defined otherwise by thecontext.

Further, the term “semiconductor integrated circuit device” as used inthe present application means a device mainly including various kinds oftransistors (active elements), such as a resistor or a capacitor,integrated on a semiconductor chip or the like (for example, amonocrystalline silicon substrate). Various types of representativetransistors can include, for example, a metal insulator semiconductorfield effect transistor (MISFET), typified by a metal oxidesemiconductor field effect transistor (MOSFET). At this time, thetypical integrated circuit structure can include, for example, acomplementary metal insulator semiconductor (CMIS) type integratedcircuit, typified by a complementary metal oxide semiconductor typeintegrated circuit with a combination of an N-channel type MISFET and aP-channel type MISFET.

A wafer process of a modern semiconductor integrated circuit device,that is, a large scale integration (LSI), can be normally classifiedbroadly into a front end of line (FEOL) process and a back end of line(BEOL) process. The FEOL process involves a delivery process of asilicon wafer as raw material, and a premetal process (includingformation of an interlayer insulating film between a lower end of a M1wiring layer and a gate electrode structure, formation of contact holes,formation of a tungsten plug, embedding, and the like). The BEOL processinvolves a formation process of the M1 wiring layer, and a formationprocess of a pad opening in a final passivation film on thealuminum-based pad electrode (which may also include a wafer levelpackage process). The gate electrode patterning process and the contacthole formation process among the FEOL process are a microfabricationprocess which requires a very fine process. In contrast, in the BEOLprocess, a via and trench formation process, especially, the formationof local wiring at a relatively low layer (for example, fine embeddedwiring layers from M1 to M3 in the case of an embedded wiring structurewith a four-layered structure, or those from M1 to M5 in the case of anembedded wiring structure with ten layers), or the like requires a veryfine process. It is noted that “MN (normally, N ranging from about 1 to15 (N=1 to 15)” represents an N-th wiring layer counted from the lowerside. The reference character M1 represents a first wiring layer, andthe reference character M3 represents a third wiring layer.

2. Likewise, in the description of the embodiments and the like, thephrase “X made of A” about material, component, or the like does notexclude a member containing an element other than A as a principalcomponent, except when specified otherwise, and except when indicatedfrom the context. For example, as to a component, the above phrase means“X containing A as a principal component” or the like. It is apparentthat for example, the term “silicon member” or the like is not limitedto pure silicon, and may have a member containing a multicomponent alloyincluding SiGe alloy or other silicon materials as a principalcomponent, and other additives or the like. Likewise, the term “siliconoxide film”, “silicon-oxide-based insulating film”, or the like includesa film made of relatively pure undoped silicon dioxide. It is apparentthat the above term also includes a thermally-oxidized film or CVD oxidefilm which is made of fluorosilicate glass (FSG), TEOS-based siliconoxide, silicon oxicarbide (SiOC), or carbon-doped silicon oxide, ororganosilicate glass (OSG), phosphorus silicate glass (PSG),borophosphosilicate glass (BPSG), or the like; a coating type siliconoxide film made of spin on glass (SOG), nano-clustering silica (NSC), orthe like; a silica-based Low-k insulating film (porous insulating film)made of the same member as that described above having holes; and acomposite film or the like containing the above-mentioned material as aprincipal component and another silicon-based insulating film.

Silicon-based insulating films generally used in the field ofsemiconductor devices include a silicon-nitride-based insulating film,in addition to the silicon-oxide-based insulating film. Materialsbelonging to such an insulating film are, for example, SiN, SiCN, SiNH,SiCNH, and the like. The term “silicon nitride” as used herein meansboth of SiN and SiNH except when specified otherwise. Likewise, the term“SiCN” as used herein means both of SiCN and SiCNH except when specifiedotherwise.

The insulating film made of SiC has properties similar to those of theinsulating film made of SiN, but the insulating film made of SiON shouldoften be classified as the silicon-oxide-based insulating film.

The silicon nitride film is used not only as an etching stopper film ina self-aligned contact (SAC) technique in many cases, but also as astress applying film in a stress memorization technique (SMT).

Similarly, the terms “copper wiring”, “aluminum wiring”, “aluminum pad”,“gold bump (gold surface film)”, and the like mean not only a membercomprised of pure material, but also a member including aluminum or goldas a principal component, that is, “copper-based wiring”,“aluminum-based wiring”, “aluminum-based pad”, and “gold-based bump(gold-based surface metal film)”, respectively. These expressions meanthat a main part of the above member is comprised of such a material asthe principal component. It is apparent that these expressions do notnecessarily mean the entire member consisting of such a material.

The same goes for the terms “barrier metal”, “seed metal”, and the like.

3. Likewise, it is apparent that preferred examples of diagrams,positions, properties, and the like are described in the embodiments,but the invention is not strictly limited thereto except when specifiedotherwise, and except when indicated otherwise from the context.

4. Further, when referring to a specific value or quantity, theinvention may have a value exceeding the specific value, or may have avalue less than the specific value except when specified otherwise,except when the invention is not limited to the value in theory, andexcept when indicated otherwise from the context.

5. The term “wafer” generally indicates a single crystal silicon waferover which a semiconductor integrated circuit device (note that the samegoes for a semiconductor device, and an electronic device) is formed,but may include a composite wafer of an insulating substrate, such as anepitaxial wafer, an SOI wafer, or a LCD glass substrate, and asemiconductor layer or the like.

6. The term “bonding pad” as used in the present application means analuminum-based pad or the like on which a multilayer metal structure orbump structure (including an area ranging from a barrier metal film to asurface metal film) is mainly formed. Suitable materials for the bondingpad may include a copper-based material as well as an aluminum-basedmaterial.

7. In the present application, a terminal electrode (electrode forexternal coupling) is formed of gold or the like by electrolytic platingor the like on a bonding pad, and has a relatively thick (as compared toa barrier metal layer or the like positioned directly below theelectrode). The terminal electrode, that is, “surface metal layer”,which is not an inherent bump electrode for direct coupling, is oftenreferred to as a “gold bump”, “bump electrode” or “bump electrodelayer”, or the like for convenience, taking into considerationsimilarity of shape. The inherent bump electrode normally has athickness of about 15 μm, whereas the surface metal layer normally has athickness of about 1 to 5 μm. In an example where an electrolytic platedlayer made of copper, nickel, or the like is formed relatively thicklyunder a gold layer as the surface metal layer, the whole surface metallayer including these layers as parts thereof has a thickness of about15 μm in some cases.

The term “bonding ball” in ball bonding as used herein means aball-shaped metal core or its deformed one formed at a first bondingpoint, and also a ball-shaped metal core or its deformed one, such as astud bump, formed due to a bonding wire.

8. In the present application, the term “wiring board” as used hereinincludes not only a general-purpose organic wiring board (monolayer andmultilayer) made of glass epoxy, or the like, but also a flexible wiringboard, a ceramic wiring board, a glass wiring board, and the like. Theterm “electronic element” on the wiring board as used herein includes asemiconductor device, a semiconductor chip, other chip components(resistor, capacitor, and the like) and the like sealed in a package.

Further Detailed Description of the Preferred Embodiments

The preferred embodiments will be further described below in detail. Ineach drawing, the same or similar part is designated by the same orsimilar reference character or numeral, and a description thereof willnot be repeated in principle.

1. Explanation of Device Cross-Sectional Structure in Completion of PadOpening Process on Aluminum-Based Pad in Semiconductor IntegratedCircuit Device of One Embodiment of Present Application (Mainly See FIG.1)

FIG. 1 is a device cross-sectional view (at the time of completion of apad opening process) showing one example of a cross-sectional structureof a device of the 65 nm technology node manufactured by a manufacturingmethod of a semiconductor integrated circuit device in one embodiment ofthe invention of the present application. Based on FIG. 1, the outlineof the device structure of the semiconductor integrated circuit devicein the embodiment of the present application will be described below.

As shown in FIG. 1, for example, a gate electrode 8 of a P-channelMOSFET or an N-channel MOSFET is formed on a device surface of a P-typemonocrystalline silicon substrate 1 isolated by a shallow trenchisolation (STI) type element isolation field insulating film 2. Overthese components, a silicon nitride liner film 4 (for example, of about30 nm in thickness) is formed to serve as an etching stopper film. Onthe film 4, a premetal interlayer insulating film 5 is formed in athickness much larger than that of the silicon nitride liner film 4. Theinsulating film 5 is comprised of an ozone TEOS silicon oxide film (forexample, of about 200 nm in thickness) formed as a lower layer by athermal CVD method, and a plasma TEOS silicon oxide film (for example,of about 270 nm in thickness) formed as an upper layer. Tungsten plugs 3are formed through the premetal insulating film. An area up to thispoint is a premetal region PM.

The first wiring layer M1 thereon is comprised of an insulating barrierfilm 14 made of a SiCN film (for example, of about 50 nm in thickness)as a lower layer, a plasma silicon oxide film 15 as a main interlayerinsulating film (for example, of about 150 nm in thickness), and copperwirings 13 or the like embedded in wiring slots formed therein.

Second to sixth wiring layers M2, M3, M4, M5, and M6 thereon havesubstantially the same structure to one another. Each layer is comprisedof a composite insulating barrier film (liner film) 24, 34, 44, 54, or64 made of a SiCO film (for example, of about 30 nm in thickness)/SiCNfilm (for example, of about 30 nm in thickness) as a lower layer, and amain interlayer insulating film 25, 35, 45, 55, or 65 occupying most ofan area as an upper layer. The main interlayer insulating film 25, 35,45, 55, or 65 is comprised of a carbon-doped silicon oxide film, thatis, a SiOC film (for example, of about 350 nm) as a lower layer, and aplasma TEOS silicon oxide film (for example, of about 80 nm inthickness) as a cap film. Copper embedded wirings 23, 33, 43, 53, or 63including a copper plug and a copper wiring are formed through theinterlayer insulating films.

Seventh and eighth wiring layers M7 and M8 thereon have substantiallythe same structure to each other. Each layer is comprised of aninsulating barrier film 74 or 84 made of a SiCN film (for example, ofabout 70 nm in thickness) and the like as a lower layer, and a maininterlayer insulating film 75 or 85 as an upper layer. The maininterlayer insulating film 75 or 85 is comprised of a plasma TEOSsilicon oxide film (for example, of about 250 nm in thickness) as alower layer, a FSG film (for example, of about 300 nm in thickness), anda USG film (for example, of about 200 nm in thickness) as a cap film.Copper embedded wirings 73 or 83 including a copper plug and a copperwiring are formed through these interlayer insulating films.

Ninth and tenth wiring layers M9 and M10 thereon have substantially thesame structure to each other. Each layer is divided into an interlayerpart as a lower layer and an intralayer part as an upper layer. Theinterlayer insulating film is comprised of an insulating barrier film 94b or 104 b made of a SiCN film (for example, of about 70 nm) or the likeas a lower layer, and a main interlayer insulating film or the like asan upper layer. The main interlayer insulating film is comprised of aFSG film 95 b or 105 b (for example, of about 800 nm in thickness) as alower layer, and a USG film 96 b or 106 b (for example, of about 100 nmin thickness) or the like which is a cap film as an upper layer. Theintralayer insulating film is comprised of an insulating barrier film 94a or 104 a made of a SiCN film (for example, of about 50 nm inthickness) or the like as a lower layer, and a main intralayerinsulating film or the like as an upper layer. The main intralayerinsulating film is comprised of a FSG film 95 a or 105 a (for example,of about 1200 nm in thickness) as a lower layer, and a USG film 96 a or106 a (for example, of about 100 nm in thickness) which is a cap film asan upper layer. Copper embedded wirings 93 or 103 including a copperplug and a copper wiring are formed through the interlayer insulatingfilm, the intralayer insulating film, and the like.

An uppermost wiring layer (pad layer) AP thereon is comprised of aninsulating barrier film made of a SiCN film 114 and the like (forexample, of about 100 nm in thickness) as a lower layer, a maininterlayer insulating film made of a USG film 117 (for example, of about900 nm in thickness) as an intermediate layer, and a final passivationfilm or the like made of a plasma SiN 119 (for example, of about 600 nmin thickness) as an outermost part. A tungsten plug 113 is providedthrough the interlayer insulating films, and an aluminum-based bondingpad 118 (for example, of about 1000 nm in thickness) is provided on theUSG film 117. The aluminum-based bonding pad 118 and the tungsten plug113 are provided with a titanium adhesive layer 151 (for example, ofabout 10 nm in thickness) as a lower layer and a titanium nitridebarrier metal layer 152 (for example, of about 30 nm in thickness) as anupper layer. A titanium nitride layer 153 (for example, of about 70 nmin thickness) is formed on the bonding pad 118, and then a bonding padopening 163 is formed in the layer 153 and the plasma SiN film 119.

Instead of the aluminum-based bonding pad 118, a copper-based bondingpad may be used.

2. Explanation of Processes Performed after Formation of Bonding PadOpening in Manufacturing Method of Semiconductor Integrated CircuitDevice in One Embodiment of Present Application (Mainly See FIG. 2,FIGS. 3 to 9, FIG. 16, FIGS. 17 to 24, and FIG. 25)

Next, the formation processes of a metal layer structure (surface metallayer, gold bump, or the like) over the bonding pad in the manufacturingmethod of the semiconductor integrated circuit device according to theembodiment of the invention of the present application will be describedbelow based on FIGS. 3 to 9, and FIGS. 17 to 24.

FIG. 2 is a process flowchart showing the flow from the pad opening stepto the wire bonding process during a manufacturing procedure of thesemiconductor integrated circuit device in the embodiment of the presentapplication. FIG. 3 is a process flowchart showing a device section (atthe time of completion of the pad opening step) of a semiconductor chip(corresponding to a section taken along the line X-X′ of FIG. 18) of thesemiconductor integrated circuit device in the embodiment of the presentapplication. FIG. 4 is a process flowchart showing a device section (ina barrier film formation step) of the semiconductor chip (correspondingto a section taken along the line X-X′ of FIG. 19) of the semiconductorintegrated circuit device in the embodiment of the present application.FIG. 5 is a process flowchart showing a device section (in a resist filmapplication step) of the semiconductor chip (corresponding to a sectiontaken along the line X-X′ of FIG. 20) of the semiconductor integratedcircuit device in the embodiment of the present application. FIG. 6 is aprocess flowchart showing a device section (in a resist film openingstep) of the semiconductor chip (corresponding to a section taken alongthe line X-X′ of FIG. 21) of the semiconductor integrated circuit devicein the embodiment of the present application. FIG. 7 is a processflowchart showing a device section (in a gold plating step) of thesemiconductor chip (corresponding to a section taken along the line X-X′of FIG. 22) of the semiconductor integrated circuit device in theembodiment of the present application. FIG. 8 is a process flowchartshowing a device section (in a resist removal step) of the semiconductorchip (corresponding to a section taken along the line X-X′ of FIG. 23)of the semiconductor integrated circuit device in the embodiment of thepresent application. FIG. 9 is a process flowchart showing a devicesection (in a barrier metal removal step) of the semiconductor chip(corresponding to a section taken along the line X-X′ of FIG. 24) of thesemiconductor integrated circuit device in the embodiment of the presentapplication. FIG. 16 is a device cross-sectional view of thesemiconductor chip (at the time of completion of a wafer processingstep) (corresponding to the section taken along the line X-X′ of FIG.25) of the semiconductor integrated circuit device according to anotherembodiment of the present application (in an example where two layeredpolyimide film is provided as an additional final passivation film).FIG. 17 is a top view of the semiconductor chip of the semiconductorintegrated circuit device in the embodiment of the present application,corresponding to FIG. 3. FIG. 18 is an enlarged top view (whosecorresponding cross-sectional view is shown in FIG. 3) of a partenclosed by a broken line in FIG. 17. FIG. 19 is an enlarged top view ofthe part enclosed by the broken line in FIG. 17 in the stepcorresponding to FIG. 4. FIG. 20 is an enlarged top view of the partenclosed by the broken line in FIG. 17 in the step corresponding to FIG.5. FIG. 21 is an enlarged top view of the part enclosed by the brokenline in FIG. 17 in the step corresponding to FIG. 6. FIG. 22 is anenlarged top view of the part enclosed by the broken line in FIG. 17 inthe step corresponding to FIG. 7. FIG. 23 is an enlarged top view of thepart enclosed by the broken line in FIG. 17 in the step corresponding toFIG. 8. FIG. 24 is an enlarged top view of the part enclosed by thebroken line in FIG. 17 in the step corresponding to FIG. 9. FIG. 25 isan enlarged top view of the step corresponding to FIG. 16.

First, as shown in FIGS. 3, 17, and 18, a final passivation film 119made of, for example, silicon nitride or the like (which is not limitedto an inorganic film, but may be an organic film) is formed on a mainsurface of a wafer 101 including a number of devices and wirings (madeof a silicon oxide, or various metal layers) formed therein under thepad (note that a polyimide resin layer 120 is often formed thereon asshown in FIG. 16). The pad opening 163 (which is an opening formed inthe final passivation film 119) is provided in a position correspondingto the aluminum pad 118 (in the pad opening step S201 shown in FIG. 2).

Then, sputtering etching is performed in an atmosphere containing argonas a principal component so as to remove a natural oxide film on thesurface of the bonding pad 118 in the state shown in FIG. 3 (in asputtering etching process at step S202 shown in FIG. 2).

Then, as shown in FIGS. 4 and 19, a barrier and seed metal layer (underbump metal film) 67 is formed by sputtering deposition. A barrier metalfilm 121 as a lower layer can be, for example, a titanium film having athickness of, for example, about 175 μm (whose thickness can bepreferably in a range of 150 to 200 μm) (in a Ti sputtering process atstep S203 shown in FIG. 2). A seed metal film 122 as an upper layer canbe, for example, a palladium film having a thickness of, for example,about 175 μm (whose thickness can be preferably in a range of about 150to 200 μm) (in a Pd sputtering process at step S204 shown in FIG. 2).

Then, as shown in FIGS. 5 and 20, a positive type resist film 12 (or anegative type one if necessary) having, for example, a thickness of 4 μm(whose thickness can be preferably in a range of about 2 to 6 μm) isformed on the film 122 (in a resist application process at step S205shown in FIG. 2).

Then, as shown in FIGS. 6 and 21, the resist is exposed (for example,exposed to i-rays), and developed (for example, by alkaline developer)to form openings 66 (in an exposure process at step S206 and adevelopment process at step S207 as shown in FIG. 2). Subsequently, anoxygen asher process (oxygen plasma process) is performed (for example,at room temperature for about 120 seconds) so as to remove organiccontaminants or the like at the bottom of the opening 66 (in an O₂ashing process at step S208 shown in FIG. 2).

Then, as shown in FIGS. 7 and 22, a gold layer serving as a surfacemetal layer (bump electrode) 115 of, for example, about 2 μm inthickness (whose thickness is preferably in a range of 1 to 5 μm) isembedded in the opening 66 by electroplating (in an electrolytic platingprocess at step S209 shown in FIG. 2). Conditions for plating can be,for example, that as to a wafer of 300 φ, a sodium gold sulfite platingsolution is used at a temperature of the solution of 55 degrees C. and acurrent value of 0.1 to 1 A/dm² for a plating time of about 20 minutes.

Thereafter, as shown in FIGS. 8 and 23, the resist film 12 is removed(in a resist removal process at step S210 shown in FIG. 2).Subsequently, the oxygen asher process (oxygen plasma process) isperformed (for example, at room temperature for about 120 seconds) inorder to remove organic contaminants or the like (in an O₂ ashingprocess at step S211 shown in FIG. 2). Finally, as shown in FIGS. 9 and24, unnecessary parts of the barrier and seed metal layer 67 (UBM film)are selectively removed in turn by wet etching using the surface metallayer (gold bump electrodes) 115 as a mask (in a Pd wet etching processat step S212 and in a Ti wet etching process at step S213 shown in FIG.2). An etching solution for the seed metal film 122 can be, for example,an iodic etching solution, and an etching solution for the barrier film121 can be, for example, a mixture of ammonia and hydrogen peroxide, orthe like. Subsequently, the oxygen asher process (oxygen plasma process)is performed (for example, at room temperature for about 120 seconds) inorder to remove organic contaminants or the like (in an O₂ ashingprocess at step S214 shown in FIG. 2).

At this time, the surface metal layer (bump electrode) is finished. Thesurface metal layer (gold bump electrode) 115 is normally comprised ofrelatively pure gold material. However, the surface metal layer can bebasically comprised of a gold-based alloy containing gold as a principalcomponent. In Section 3, the following steps and the like for the partenclosed by a broken line in FIG. 9 will be described later.

The barrier metal film can include one selected from the groupconsisting of titanium, chromium, titanium nitride, and tungsten nitrideas a principal component. The barrier metal film is required to have thecapability of sputtering deposition, and adequate barrier propertyagainst gold.

Further, the seed metal film can be comprised of one selected from thegroup comprising copper, gold, nickel, platinum, rhodium, molybdenum,tungsten, chromium, and tantalum as a principal component. The seedmetal film is required not to react with the barrier metal film, not toform a fragile reaction layer by reaction with gold, and to be such alow-resistance material that allows an electrolytic gold layer to grow.

FIG. 16 is a modified example corresponding to the structure describedwith reference to FIGS. 3 to 9, and the like. In an example shown inFIGS. 16 and 25, after patterning the plasma SiN film (inorganic finalpassivation film on the pad) 119, the polyimide film 120 which is anorganic passivation film is formed thereon, and then patterned (to forman opening 123 in the polyimide film). This example is subjected to thecomplicated processes and thus has the complicated structure, but has anadvantage in improvement of reliability. Instead of, or in addition tothis structure, the inorganic final passivation film 119 can becomprised of an inorganic insulating film as a lower layer and apolyimide film as an upper layer.

3. Explanation of Assembly Processes and Device Structure inManufacturing Method of Semiconductor Integrated Circuit Device in OneEmbodiment of Present Application (See FIGS. 10 to 12, in Addition toFIGS. 2 and 9, and the Like)

In this section, the procedure following the processes described inSection 2 from the O₂ ashing process at step S214 to the wire bondingprocess at step S219 (formation of a stud bump in use thereof) shown inFIG. 2 will be described below.

FIG. 10 is a top view of the semiconductor chip of the semiconductorintegrated circuit device in the embodiment of the present application,corresponding to FIG. 9. FIG. 11 is a top view of the semiconductorintegrated circuit device in the embodiment of the present application.FIG. 12 is an exemplary cross-sectional view corresponding to a partenclosed by a broken line of FIG. 11.

As shown in FIG. 2, after the O₂ ashing process in step S214 (see FIG.2) described with reference to FIG. 9 (FIG. 16), a probe test 215 (waferinspection) is performed on the wafer 101. Thereafter, the back side ofthe wafer 101 is grounded into a predetermined thickness, that is,subjected to back grinding in a BG process at step S216. Subsequently, adicing process is performed which involves dividing the wafer 101 intochips 101 using a laser, a rotation blade, or both thereof in step S217.The state of the chips 101 divided is shown below.

FIG. 10 is a top entire view of the semiconductor chip 101 of thesemiconductor integrated circuit device in the embodiment of the presentapplication, corresponding to FIG. 9 (or FIG. 16). In the figure, thesemiconductor chip 101 has substantially the entire surface thereofcovered with the final passivation film 119 (120), and the surface metallayer 115 is provided on each pad of the periphery of the film.

Then, as shown in FIGS. 11 and 12 (enlarged cross-sectional view of thepart enclosed by the broken line of FIG. 11), the semiconductor chip 101is die-bonded over a wiring board 133 (which may be a ceramic substrate,a flexible wiring board, or the like), which is an organic multilayerwiring board or the like (may be a single layer wiring board), via theadhesive layer 130 (die attach film, paste, or the like) (in a diebonding process at step S218 shown in FIG. 2).

Then, as shown in FIG. 12, the use of a bonding wire 132 and a bondingcapillary 171 including gold as a principal component couples thesurface metal layer 115 (metal surface) over the bonding pad 118 on thechip (die) 101 to a lead portion 131 outside the chip 101 (in this case,on the wiring board 133) (in the wire bonding process at step S219 at abonding temperature of, for example, about 150 degrees as shown in FIG.2). In this case, the surface metal layer 115 side is subjected to ballbonding (at a primary ball bonding portion 135) together with a ball134, and the lead portion 131 side is subjected to wedge bonding (at asecondary bonding portion 136) (note that both portions are regarded asone set and referred to as “ball bonding”, “ball wedge bonding”,“nailhead bonding”, or the like). The type of bonding is preferably athermo-sonic bonding process (using a combination of heating andultrasonic energy) from the requirement of reduction in temperature.Bonding using the ball 134 on the chip side in this way (the way inwhich the chip side serves as the secondary bonding portion) isespecially referred to as “forward bonding” so as to be distinguishedfrom “reverse bonding” shown in FIG. 14 as described in the followingsection.

In this embodiment, a surface metal layer including gold as a principalcomponent is formed over the aluminum based (or copper based) bondingpad on the semiconductor chip side, whose properties are not uncertain,via an intermediate metal layer comprised of barrier metal and the like.Even when the gold-based bonding wire including gold as a principalcomponent (for example, which may contain palladium and other additives)is used for interconnection with the wiring board and the like, theprogress of an undesired reaction due to the use at high temperature fora long time can be avoided.

The surface of the lead portion 131 is desirable as a so-called bondingmetal film (metal film including gold, silver, palladium, or an alloythereof as a principal component) from the viewpoint of the reliability.

4. Explanation of Modified Example of Assembly Process and DeviceStructure in Manufacturing Method of Semiconductor Integrated CircuitDevice in One Embodiment of Present Application (See FIGS. 13 to 15)

Various modified examples regarding the assembly process and assemblystructure described in Section 3 will be described below.

FIG. 13 is an exemplary cross-sectional view showing an example in whichthe order of wire bonding is changed from that in FIG. 12. FIG. 14 is anexemplary cross-sectional view showing an example in which the wiringboard is replaced by another electronic element on the wiring board inFIG. 12. FIG. 15 is an exemplary cross-sectional view showing an examplein which a target part of the semiconductor chip to be die-bonded isreplaced by a further electronic elements (flip-chip bonded) onto thewiring board in FIG. 12.

(1) Explanation of Reverse Bonding System (Backward Bonding) (See FIG.13)

As shown in FIG. 13, the order of the wire bonding shown in FIG. 12 maybe reversed. That is, the reverse bonding may be employed. In this case,the surface metal layer 115 side is the secondary bonding portion 136,which has a merit of reduction in height of a wire loop. The normaldirect bonding to the aluminum bonding pad 118 has problems of impact onthe device. However, in this example, the presence of the relativelythick surface metal layer 115 relatively reduces the influences on theabove problems.

Like Section 3, the surface of the lead portion 131 is desired to havethe so-called bonding metal film (metal film including gold, silver,palladium, or an alloy thereof as a principal component) from theviewpoint of reliability.

(2) Explanation of Wire Bonding System Between Two Chips (See FIG. 14)

In this example as shown in FIG. 14, unlike FIGS. 12 and 13, thesemiconductor chip 101 is die-bonded not directly on a wiring board 133,but over another semiconductor chip 101 b (more widely, a device chip)on the wiring board 133, that is, an underlayer chip (underlayerelectronic element, hereinafter referred to as the same). In the casewhere the surface metal layer 115 on the semiconductor chip 101 isinterconnected to the surface metal layer 115 on the underlayer chip 101b via the bonding wire 132, when another semiconductor chip 101 b hasthe same multilayer metal structure on the pad as that of thesemiconductor chip 101, both bonding portions have the structures withhigh reliability.

The reverse bonding can also be applied.

(3) Explanation of Flip Chip Die Bonding Type (See FIG. 15)

As shown in FIG. 15, the die bonding of the semiconductor chip 101 maybe performed over another semiconductor chip 101 b which is flip-chipbonded to the wiring board 133 (bonded to land electrodes 138 for solderbump on the wiring substrate 133 by solder bumps 137), that is, over anunderlayer chip. In this case, the interconnection by the bonding wire132 is performed at the surface metal layer 115 over the semiconductorchip 101, an electrode (lead portion) on the device chip other than theunderlayer chip 101 b, or the lead portion 131 on the wiring board 133.

Like the description in Section 3, the surface of the lead portion 131is desired to be the so-called bonding metal film (metal film includinggold, silver, palladium, or an alloy thereof as a principal component)from the viewpoint of the reliability.

The reverse bonding can also be applied.

5. Explanation of Various Package Forms of Semiconductor IntegratedCircuit Device in One Embodiment of Present Application (Mainly SeeFIGS. 38 to 44)

In this section, various package forms of the semiconductor integratedcircuit device in one embodiment of the present application (note thatthe same goes for other embodiments) will be described below.

FIG. 38 is an entire top view of the semiconductor integrated circuitdevice (wire bonding type BGA) at the time of completion of a packagingprocess in the embodiment of the present application (omittingillustration of a resin sealing member for easy understanding). FIG. 39is an exemplary cross-sectional view of FIG. 38. FIG. 40 is an entiretop view of the semiconductor integrated circuit device (QFP: Quad FlatPackage) at the time of completion of a packaging process in theembodiment of the present application (omitting illustration of an upperhalf part of the resin sealing member for easy understanding). FIG. 41is an exemplary cross-sectional view of FIG. 40. FIG. 42 is an entiretop view of the semiconductor integrated circuit device (flip-chip typeBGA) at the time of completion of a packaging process in the embodimentof the present application. FIG. 43 is an exemplary cross-sectional viewof FIG. 42. FIG. 44 is an enlarged cross-sectional view of the partenclosed by a broken line of FIG. 43.

First, based on FIGS. 38 and 39, the wire bonding type BGA using thewiring board 133 (for example, organic multilayer wiring board) will bedescribed below. As shown in FIGS. 38 and 39, the device chip 101(semiconductor chip) is die-bonded over the wiring board 133 via anadhesive layer 130 (for example, a die attach film or a die bond paste,or the like). A plurality of surface metal layers 115 (on the bondingpad) are provided over the upper surface of the device chip 101, and arecoupled to a plurality of outer leads 131 provided on the upper surfaceof the wiring board 133 via the bonding wires 132. In this example,bonding balls 134 are made on the surface metal layer 115 side. Theupper surface of the wiring board 133 is sealed with a sealing resin181. In contrast, a plurality of solder bumps 137 are provided on thelower surface side of the wiring board 133.

Next, based on FIGS. 40 and 41, a wire bonding type QFP (a resin packageusing a lead frame) will be described below. As shown in FIGS. 40 and41, the device chip 101 (semiconductor chip) is die-bonded via theadhesive layer 130 (for example, a die attach film or a die bond paste,or the like) over a die pad 145 held by four die pad support bars 146. Aplurality of surface metal layers 115 (on the bonding pad) are providedover the upper surface of the device chip 101, and are coupled to leadportions 131 by the bonding wires 132. In this example, bonding balls134 are made on the surface metal layer 115 side. The inside of the lead131, the die pad support bars 146, the die pad 145, the device chip 101,and the bonding wires 132 are sealed with a resin sealing member 181(sealing resin).

Further, the flip chip type BGA (for example, flip chip bonding by goldbased stud bump) will be described below based on FIGS. 42 to 44. Asshown in FIGS. 42 to 44, a plurality of land pads 155 are provided onthe wiring board 133. Gold stud bumps 157 (which may be copper-basedone) under the surface metal layers 115 (bonding pads) on the lowersurface of the device chip 101 are coupled to the land pads 155 via asolder layer 156 (for example, lead-free solder or the like comprised of3.5% by weight silver and a balance including tin). The coupling isreinforced by an underfill resin 148 (for example, an epoxy resincontaining silica powder or the like). Solder bumps 137 for externalcoupling (for example, lead-free solder comprised of 3.5% by weightsilver, 0.5% by weight copper, and a balance including tin) are providedon the lower surface of the wiring board 133.

6. Explanation of Wafer Probe Inspection in Manufacturing Method ofSemiconductor Integrated Circuit Device or the Like in One Embodiment ofPresent Application (Mainly See FIGS. 27 to 32)

This section will further describe the probe test 215 and the wirebonding process at step S219 which has been described above in Section 3based on FIG. 2.

FIG. 27 is an enlarged view of a top surface of a wafer (square pad in afirst example) showing a state of the wafer probe test process in themanufacturing procedure of the semiconductor integrated circuit devicein the embodiment of the present application. FIG. 28 is an enlargedview of the top surface of the wafer (square pad in the first example)at the time of completion of the wire bonding process in the examplecorresponding to FIG. 27. FIG. 29 is an enlarged view of a top surfaceof another wafer (normal type rectangular pad in a second example)showing the state of the wafer probe test process in the manufacturingprocedure of the semiconductor integrated circuit device in theembodiment of the present application. FIG. 30 is an enlarged view ofthe top surface of the wafer (normal rectangular pad in the secondexample) at the time of completion of the wire bonding process in theexample corresponding to FIG. 29. FIG. 31 is an enlarged view of a topsurface of a further wafer (modified rectangular pad in a third example)showing the state of the wafer probe test process in the manufacturingprocedure of the semiconductor integrated circuit device in theembodiment of the present application. FIG. 32 is an enlarged view ofthe top surface of the wafer (modified rectangular pad in the thirdexample) at the time of completion of the wire bonding process in theexample corresponding to FIG. 31. Based on the above description, therelationship or the like among the shapes of the bonding pad and thesurface metal layer (also including the orientation), a probe needle,and the bonding wire will be described below.

First, the probe test process using the square pad at step S215 (seeFIG. 2) will be described below based on FIG. 27. As shown in FIG. 27,the surface metal layer 115 and the bonding pad 118 are concentricallypositioned (substantially sharing the center) with the homothetic shape(note that in this case, the bonding pad 118 is slightly larger thanthat of the metal layer 115). Parts other than the surface metal layer115 and the bonding pad 118 are almost covered with a plasma SiN 119(inorganic final passivation film on the pad) or the like. In the probetest 215, a plurality of probe needles 221 are in contact with therespective surface metal layers 115. The surface metal layer 115comprised of gold-based metal material (metal including high-puritygold, or gold as a principal component) has excellent contactability.This is because the gold-based metal material hardly generates a naturaloxide film on its surface, which inevitably leads to reduced contactdamage (also resulting in relatively small contact load and over-driveamount). This is effective especially in use of a Low-k film or the likewhich is mechanically fragile, as a wiring interlayer insulating filmunder the pad.

Now, the wire bonding process at step S219 by use of the square pad willbe described below based on FIG. 28. As shown in FIG. 28, in this case,bonding of the bonding wire 132 (bonding balls 134) is performed in thesame position as the position with which the probe needle 221 is broughtinto contact in the probe test process at step S215. The presence of thesurface metal layer 115 has the merit of not causing adverse effect onbonding properties because of small contact damage (without leaving somuch as a contact trace), unlike the case where the contact trace isleft due to peeling of an Al pad.

The probe test process at step S215 and the wire bonding process at stepS219 (see FIG. 2) using the normal rectangular pad will be describedbelow based on FIGS. 29 and 30. As shown in FIGS. 29 and 30, the surfacemetal layer 115 and the bonding pad 118 are concentrically positioned(substantially sharing the center) with the homothetic shape as viewedplanarly (note that in this case, the bonding pad 118 is slightly largerthan that of the metal layer 115). In this embodiment, however, sincethe surface metal layer 115 and the bonding pad 118 are rectangular,wire bonding can be performed in a position different from the positionwith which the probe needle 221 is in contact. Thus, in various kinds ofprobe tests, for example, repeated inspection (re-inspection) processesor the like are performed. Even when the contact damage may becomerelatively large, the influence on the wire bonding can be avoided.

Next, the probe test process at step S215 and the wire bonding processat step S219 (see FIG. 2) using a modified rectangular pad will bedescribed based on FIGS. 31 and 32. As shown in FIGS. 31 and 32, thesurface metal layer 115 has a rectangular shape, and the bonding pad 118has a substantially square shape as viewed planarly. The layer 115 andthe pad 118 are partially superimposed on each other, but displaced fromeach other, in terms of orientation or positional relationship. A partof each surface metal layer 115 without the bonding pad 118 is formedover the plasma SiN (inorganic final passivation film on the pad) 119via the under bump metal layer (barrier and seed metal layer) 67.Therefore, the same merits as those of the above-mentioned normalrectangular pad can be obtained. In general, a cushion material (impactbuffer layer), such as the bonding pad 118 desirably exists under a partto be probed. The surface metal layer 115 comprised of gold-based metalmaterial can ensure its hardness, and can reduce the contact damage to arelatively small level in many cases. Thus, even when the probe needle221 is in contact with the part of the layer 115 without the bonding pad118 under the part as shown in FIG. 31, the damage to the lower plasmaSiN film (inorganic final passivation film on the pad) 119 can bereduced. Wire bonding points can be provided in positions for allowingbonding on the surface metal layer 115. As shown in FIG. 32, the wirebonding points are set in the part with the bonding pad 118 thereby toenable reduction in probability of occurrence of the damage.

7. Explanation of Metal Layer Structure (or Under Bump Metal Structure)Under Each Type of Surface Metal Layer of Semiconductor IntegratedCircuit Device in One Embodiment of Present Application (Mainly SeeFIGS. 45 to 47)

Various types of metal layer structures under the surface metal layer asdescribed above will be further described in more detail.

FIG. 45 is a cross-sectional view of the periphery of the pad forexplaining one type of underbumb metal structure (two-layered structure)in the semiconductor integrated circuit device of one embodiment of thepresent application. FIG. 46 is a cross-sectional view of the peripheryof the pad in a modified example of FIG. 45. FIG. 47 is across-sectional view of the periphery of the pad for explaining anothertype of underbumb metal structure (three or more-layered multilayerstructure) in the semiconductor integrated circuit device of oneembodiment of the present application.

First, based on FIG. 45, the metal layer structure under the basicsurface metal layer of the semiconductor integrated circuit device inthe embodiment of the present application will be described below. Inthis case, as shown in FIG. 45, for example, the barrier metal film 121including titanium as a principal component is laminated on thealuminum-based bonding pad 118 (for example, in a thickness of about0.175 μm by sputtering deposition). On the barrier metal film, the seedmetal film 122 including palladium as a principal component is laminated(for example, in a thickness of about 0.175 μm by the sputteringdeposition). Then, on the metal film 122, an electrolytic gold platedbump electrode 115 (gold bump, surface metal layer, or overpad metal)including gold as a principal component is laminated (for example, in athickness of about 2.8 μm, for example, in a range of about 1 to 3 μm).The titanium film 121 is an interdiffusion barrier film against aluminumand gold. The palladium film 122 is a seed film for forming theelectrolytic gold plated surface metal layer 115.

Referring to FIG. 46, a modified one of the example shown in FIG. 45will be described below. As shown in FIG. 46, this structure includes anelectrolytic nickel plated layer 127 (whose thickness is, for example,about 2 μm) intervening between the seed metal film 122 and theelectrolytic gold plated surface metal layer 115. Nickel is harder thangold or the like, which effectively reduces the damage due to the wirebonding.

Based on FIG. 47, one example of the under bump metal structure withthree or more-multilayered structure will be described below. In thiscase, as shown in FIG. 47, for example, the barrier metal film 124including chrome as a principal component is laminated on thealuminum-based bonding pad 118 (for example, in a thickness of about0.075 μm by sputtering deposition). On the barrier metal film, a seedmetal film 125 including copper as a principal component is laminated(for example, in a thickness of about 0.25 μm by the sputteringdeposition). Then, an electrolytic copper plated layer 126 includingcopper as a principal component is laminated on the metal film 125 (forexample, in a thickness of about 2 μm, for example, in a range of about1 to 10 μm if necessary). Further, on the plated layer 126, anelectrolytic nickel plated layer 127 including nickel as a principalcomponent is laminated (in the thickness of about 2 μm). On the platedlayer 127, an electrolytic gold plated bump electrode 115 including goldas a principal component (gold bump, surface metal layer, or overpadmetal film) is laminated (in a thickness of about 2.8 μm, for example,in a range of about 1 μm to about three μm). The chrome film 124 is aninterdiffusion barrier film against aluminum and copper. The copper film125 is a seed film for forming the electrolytic copper plated film 126.

This structure has the features that the nickel layer and the copperlayer which are relatively thick and hard are formed under theelectrolytic gold plated bump electrode 115, and thus can effectivelyreduce the damage due to the wire bonding. Additionally, the structurecan be used as a wiring line (re-wiring line with a low resistance)comprised of the nickel layer and the copper layer with highreliability. Further, the structure can also effectively reduce theresistance of an external terminal.

8. Consideration Regarding Various Embodiments (Mainly See FIG. 26, andFIGS. 33 to 37)

This section will provide a description or another supplementaldescription of the features and technical effects or the like common toor specific to the respective embodiments.

FIG. 26 is an explanatory cross-sectional view for explaining problemsof nonelectrolytic gold plating on a nickel surface. FIG. 33 is a localexemplary cross-sectional view of an aluminum pad and a bonding wire forexplaining Kirkendall Void caused in bonding between aluminum and gold.FIG. 34 is a local cross-sectional view showing one of various examples(normal mode) of a bonded state of the bonding wire on the pad at thesemiconductor integrated circuit device in the embodiment of the presentapplication. FIG. 35 is a local cross-sectional view showing one ofvarious examples (lateral sliding mode 1) of a bonded state of thebonding wire on the pad in the semiconductor integrated circuit deviceof the embodiment of the present application. FIG. 36 is a localcross-sectional view showing one of various examples (lateral slidingmode 2) of a bonded state of the bonding wire on the pad in thesemiconductor integrated circuit device of the embodiment of the presentapplication. FIG. 37 is a local cross-sectional view for explaining therelationship among various dimensions of a bonded structure of thebonding wire on the pad at the semiconductor integrated circuit devicein the embodiment of the present application.

First, the problems with the use of nonelectrolytic gold plating (whichis not limited to gold, and thus may be replaced by copper or nickel),instead of the electrolytic gold plating, will be described based onFIG. 26 by taking the case of the nonelectrolytic gold plating(displacement gold plating) on a nickel surface 301 as an example. Asshown in FIG. 26, the nonelectrolytic gold plated film is formed byattaching a gold member 302 to a part 303 lacking nickel as underlyingmetal. Gold plated areas 302 themselves are in the porous state becausea plating reaction is stopped while covering the surface. Then, nickelelements are apt to be easily deposited from the porous parts, and thedeposited nickel elements are oxidized to form nickel oxides (NiO). Thepresence of the nickel oxide on the gold plating area 302 makes itdifficult to bond the bonding wire, and causes the wire to be easilypeeled off even if the wire is attached. Since the plating reaction isstopped on a stage where the gold plated areas 302 cover the surface, itis generally difficult to ensure the plating thickness of about 100 nm(or about 0.1 μm) or more. Further, an interface between the nickelsurface 301 and the gold plated areas 302 has voids formed therein, andthus cannot ensure adequate bonding (adhesive) property, which easilycauses peeling of a gold layer (interfacial peeling).

In contrast, in the electrolytic plating process, the plating reactionproceeds by an electric field from the external side, and can form adense plated film, and further can make the formed plating film thickerthan that of a film subjected to the nonelectrolytic gold plating. It isapparent that this is not limited to the case where an underlayer ismade of nickel.

Based on FIG. 33, the following describes the problems with directbonding of a bonding wire of gold-based material or the like (or bondingballs) to the aluminum-based pad without the surface metal layer 115 ofgold-based material or the like on the aluminum pad. When the bondingwire made of gold-based material or the like is held under a relativelylow temperature (for example, of about 150 degrees C.) for a long timewhile being directly coupled to the aluminum-based pad, as shown in FIG.33, Au—Al based intermetallic compound layers 140, 141, 142 and 143 (forexample, Au₄Al layer 140, Au₂Al layer 141, Au₅Al₂ layer 142, and AuAl₂layer 143) appear near the interface between the aluminum material andgold material. Together with the state, voids 139 (Kirkendall Void) aregenerated on a bonding ball 134 side, which may cause break ofconnection or coupling. This is because the diffusion velocity of goldelement into the Au—Al based intermetallic compound layers 140, 141,142, and 143 is much faster than that of aluminum element into the Au—Albased intermetallic compound layers 140, 141, 142, and 143. That is,gold ions move to the aluminum pad 118 at high speed, which results ingenerating a number of vacancies to be gradually condensed into voids.

In contrast, the intervention of the surface metal layer 115 ofgold-based material or the like over the aluminum pad 118 via thebarrier layer can ensure the bonding property, and also effectivelyprevent the occurrence of voids.

Based on FIGS. 34 to 36, the following describes various types ofbonding modes of the gold-based (or copper-based) bonding wire 132 or115(or bonding ball 134) to the surface metal layer 115 comprised ofgold-based material or the like. FIG. 34 shows a normal mode. That is,the bonding ball 134 is accommodated within an upper surface of thesurface metal layer 115. The example shown in FIG. 35 is one of slidingmodes in which a main bonding portion (center of the ball) of thebonding ball 134 is accommodated within the upper surface of the surfacemetal layer 115. This mode is not problematic from the viewpoint ofproperties. The example shown in FIG. 36 is another sliding mode inwhich a main bonding portion (center of the ball) of the bonding ball134 is accommodated within the upper surface of the surface metal layer115 with the ball 134 itself deformed or the ball 134 changing the shapeof the end of the surface metal layer 115, so that the lower end of theball 134 reaches the surface of a plasma SiN film (inorganic finalpassivation film on the pad) 119. Also, in this case, cracks or the likerarely occur in the plasma SiN (inorganic final passivation film on thepad) 119 or the like because of the shock absorption effect of thesurface metal layer 115. There are few problems with the properties ofproducts. Accordingly, the main features described above can be appliedto any one of the cases shown in FIGS. 34 to 36. In other words, in thecases shown in FIGS. 34 to 36, the main part of the wire bonding portioncan be located substantially directly above the bonding pad as a whole.

Now, referring to FIG. 37 (FIGS. 28, 30, 32, and 45 to 47), the bondingstructure of the bonding wire on the pad in the semiconductor integratedcircuit device of each embodiment of the present application, that is,the relationship among various dimensions of an over pad metalstructure, will be described below. As shown in FIG. 37, in the normallayout (normal structure), the width LP of the pad is largest in alldirections, the width LW of a pad opening is smallest in all directions,and the width LB of the surface metal layer is middle in all directions.Thus, as viewed planarly, the surface metal layer 115 is located withinthe bonding pad 118 (note that the surface metal layer 115 is smallerthan that of the pad in terms of area). Likewise, the bonding padopening 163 is located within the surface metal layer 115 (note that thebonding pad opening 163 is smaller than that of the metal layer in termsof area).

The abnormal structure shown in FIG. 32 only satisfies such sizerelationship and inclusive relationship in the specific lateraldirection, and does not entirely satisfy those relations in thelongitudinal direction.

Likewise, as shown in FIG. 37, in the normal structure, the thickness TBof the surface metal layer (or the thickness equivalent thereto) islarger than the thickness TU of the barrier metal layer (in general, thethickness of the barrier metal film 121). The reason why the surfacemetal layer 115 is relatively thick in this way is that the metal layer115 is to substantially ensure the properties or functions of thebonding pad. However, the thickness TB of the surface metal layer issupposed to become substantially the same as the thickness TU of thebarrier metal layer by changing peripheral parameters or the like. Boththicknesses may have the reverse relationship. Thus, the surface metallayer is not limited to the electrolytic plated one, but may be formedby sputtering deposition or nonelectrolytic plating when the surfacemetal layer is thin or partly formed. In particular, the sputteringdeposition is a process method involving photoetching the film formedover the entire wafer, which has demerits of generation of anunnecessary (disposed) part, and warpage of the wafer due to stronginternal stress in the film in many cases. But the method has a merit ofbeing capable of forming a very clean film as compared to the platedfilm.

As shown in FIGS. 46 and 47, when electrolytic metal layers are formedover the barrier metal layer 121 (or barrier and seed metal layer 67),the entire thickness of these electrolytic metal layers is theoreticallyconsistent with the thickness TB of the surface metal layer. When theseed metal layer (made of, for example, copper), and the upperelectrolytic plated layer (made of, for example, copper) are of the samequality, in fact, the seed metal layer is preferably adapted to form apart of the electrolytic plated layer in the thickness direction.

Referred to FIG. 37, the width LB of the surface metal layer can belarger than the width LP of the pad in a certain orientation ordirection like FIG. 32. Such a structure can enhance flexibility inbonding point (position for the wire bonding). Likewise, the width LB ofthe surface metal layer can be larger than the width LP of the pad inall orientations or directions. Further, the width LB of the surfacemetal layer can be smaller than the width LW of the pad opening in acertain orientation or direction (or in all orientations or directions).This structure can have merits of reducing the amount of consumption ofgold, and increasing the flexibility in various layouts.

9. Summary

Although the invention made by the inventors has been specificallydescribed based on the preferred embodiments, the invention is notlimited thereto. It will be apparent to those skilled in the art thatvarious modifications can be made to the presently disclosed embodimentswithout departing from the scope of the invention.

For example, although this embodiment has specifically described thesemiconductor chip with a damascene interconnection, such as a copperdamascene interconnection, (embedded wiring containing copper, silver,or the like as a principal wiring element), the invention is not limitedthereto. It is apparent that the invention can also be applied to theuse of a semiconductor chip with aluminum-based normal wiring(non-embedded wiring).

In the above embodiments, material for the bonding wire or bonding ball(including stud bumps) is mainly, for example, a gold-based wire. Itwill be apparent that the bonding wire can be applied to the gold-basedwire (high-purity gold, or gold with various kinds of additives addedthereto), a copper-based wire (high-purity copper, oxygen-free copper,or copper with various kinds of additives added thereto), apalladium-based wire (metal material containing palladium as a principalcomponent), or the like in the same way.

1-20. (canceled)
 21. A semiconductor device, comprising: (a) analuminium-based or a copper-based pad electrode provided over a devicesurface of a semiconductor chip; (b) an insulating film formed over thedevice surface of the semiconductor chip and in which an opening isformed such that a part of the pad electrode is exposed from theopening; (c) a barrier metal film provided over the part of the padelectrode exposed from the opening of the insulating film and a partthereof being contacted with a top surface of the insulating film; (d) asurface metal film provided over the barrier metal film and includinggold as a principal component, a film thickness of the surface metalfilm being greater than a film thickness of the barrier metal film; and(e) a bonding ball bonded to the surface metal film and including goldor copper as a principal component, wherein, in one cross-sectional viewperpendicular to the device surface, a width of the surface metal filmis greater than a width of the opening of the insulating film.
 22. Thesemiconductor device according to claim 21, wherein, in the onecross-section view, a width of the barrier metal film is greater than awidth of the opening of the insulating film.
 23. The semiconductordevice according to claim 22, wherein, in the one cross-section view,the width of the surface metal film and the width of the barrier metalfilm are the same.
 24. The semiconductor device according to claim 23,wherein the part of the barrier metal film is contacted with a portionof the top surface of the insulating film around the opening in the topsurface of the insulating film.
 25. The semiconductor device accordingto claim 21, wherein a seed metal film is formed between the barriermetal film and the surface metal film.
 26. The semiconductor deviceaccording to claim 25, wherein, in the one cross-section view, widths ofthe barrier metal film, the seed metal film, and the surface metal filmare the same.
 27. The semiconductor device according to claim 25,wherein the seed metal film includes palladium as a principal component.28. The semiconductor device according to claim 25, wherein the seedmetal film includes one selected from the group consisting of copper,gold, nickel, platinum, rhodium, molybdenum, tungsten, chrome, andtantalum as a principal component.
 29. The semiconductor deviceaccording to claim 21, wherein, in another cross-section viewperpendicular to the device surface, a width of the surface metal filmis greater than a width of the pad electrode.
 30. The semiconductordevice according to claim 21, wherein the opening of the insulating filmover the pad electrode is located within the surface metal film in planview.
 31. The semiconductor device according to claim 21, wherein thesurface metal film is formed by electrolytic plating or sputtering. 32.The semiconductor device according to claim 21, wherein the surfacemetal film is formed by nonelectrolytic plating.
 33. The semiconductordevice according to claim 21, wherein a center of the bonding ball isset over a top surface of the surface metal film.
 34. The semiconductordevice according to claim 21, wherein the bonding ball is a part of abonding wire.
 35. The semiconductor device according to claim 21,wherein the barrier metal film includes titanium as a principalcomponent.
 36. The semiconductor device according to claim 21, whereinthe barrier metal film includes one selected from the group consistingof titanium, chrome, titanium nitride, and tungsten nitride as aprincipal component.
 37. The semiconductor device according to claim 21,wherein the pad electrode has a square shape in a plan view.
 38. Thesemiconductor device according to claim 21, wherein the pad electrodehas a rectangular shape in a plan view.
 39. A semiconductor device,comprising: (a) a first-metal based pad electrode provided over a devicesurface of a semiconductor chip; (b) an insulating film formed over thedevice surface of the semiconductor chip and in which an opening isformed such that a part of the pad electrode is exposed from theopening; (c) a barrier metal film provided over the pad electrodeexposed from the opening of the insulating film and a part thereof beingcontacted with a top surface of the insulating film; (d) a surface metalfilm provided over the barrier metal film and including gold as aprincipal component, a film thickness of the surface metal film beinggreater than a film thickness of the barrier metal film; and (e) abonding ball bonded to the surface metal film, and including a secondmetal as a principal component, wherein, in one cross-sectional viewperpendicular to the device surface, a width of the surface metal filmis greater than a width of the opening of the insulating film.
 40. Thesemiconductor device according to claim 39, wherein the first metal isaluminium and the second metal is copper.